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DTSTART:18871231T000000
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BEGIN:VEVENT
DTSTAMP:20230103T035307Z
LOCATION:Auditorium\, Level 5\, West Wing
DTSTART;TZID=Asia/Seoul:20221206T100000
DTEND;TZID=Asia/Seoul:20221206T120000
UID:siggraphasia_SIGGRAPH Asia 2022_sess153_papers_448@linklings.com
SUMMARY:ICARUS: A Specialized Architecture for Neural Radiance Fields Rend
 ering
DESCRIPTION:Technical Papers\n\nICARUS: A Specialized Architecture for Neu
 ral Radiance Fields Rendering\n\nRao, Yu, Wan, Zhou, Zheng...\n\nThe pract
 ical deployment of Neural Radiance Fields (NeRF) in rendering applications
  faces several challenges, with the most critical one being low rendering 
 speed on even high-end graphic processing units (GPUs). In this paper, we 
 present ICARUS, a specialized accelerator architecture tailored for NeRF r
 endering. Unlike GPUs using general purpose computing and memory architect
 ures for NeRF, ICARUS executes the complete NeRF pipeline using dedicated 
 plenoptic cores (PLCore) consisting of a positional encoding unit (PEU), a
  multi-layer perceptron (MLP) engine, and a volume rendering unit (VRU). A
  PLCore takes in positions \& directions and renders the corresponding pix
 el colors without any intermediate data going off-chip for temporary stora
 ge and exchange, which can be time and power consuming. To implement the m
 ost expensive component of NeRF, i.e., the MLP, we transform the fully con
 nected operations to approximated reconfigurable multiple constant multipl
 ications (MCMs), where common subexpressions are shared across different m
 ultiplications to improve the computation efficiency. We build a prototype
  ICARUS using Synopsys HAPS-80 S104, a field programmable gate array (FPGA
 )-based prototyping system for large-scale integrated circuits and systems
  design. We evaluate the power-performance-area (PPA) of a PLCore using 40
 nm LP CMOS technology. Working at 400 MHz, a single PLCore occupies 16.5 $
 mm^2$ and consumes 282.8 mW, translating to 0.105 uJ/sample. The results a
 re compared with those of GPU and tensor processing unit (TPU) implementat
 ions.\n\nRegistration Category: FULL ACCESS, EXPERIENCE PLUS ACCESS, EXPER
 IENCE ACCESS, TRADE EXHIBITOR\n\nLanguage: ENGLISH\n\nFormat: IN-PERSON
URL:https://sa2022.siggraph.org/en/full-program/?id=papers_448&sess=sess15
 3
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